1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to a nonvolatile ferroelectric memory, for example.
2. Description of the Related Art
At present, semiconductor memories are used in various fields ranging from main memories of large-scale computers to personal computers, home electrical appliances, mobile telephones and the like. Various types of semiconductor memories such as volatile DRAMs (Dynamic Random Access Memories), SRAMs (Static RAMs), nonvolatile MROMs (Mask Read Only Memories) and flash EEPROMs (Electrically Erasable Programmable ROMs) are put on the market. Particularly, the DRAM is excellent in the high operation speed and dominantly controls the market because of the low cost thereof (the cell area is ¼ times that of the SRAM) although it is a volatile memory. The rewritable nonvolatile flash EEPROM can store information even after the power supply is turned OFF. However, since the flash memory has disadvantages that the number of rewriting operations (the number of W/E operations) is approximately 106, the write time is approximately several micro seconds and application of high voltage (12V to 22V) is required for writing, it is not put on the market as wisely as the DRAM.
On the other hand, a nonvolatile ferroelectric memory using a ferroelectric capacitor is nonvolatile and has advantages that the number of rewriting operations is approximately 1012, the read/write time is approximately equal to that of the DRAM and low operation voltage of 3V to 5V is used. Therefore, the nonvolatile ferroelectric memories have a possibility of occupying the whole memory market and various makers have studied and developed the nonvolatile ferro-electric memories since they were proposed in 1980.
FIG. 44 shows memory cells with the one-transistor/one-capacitor configuration of the conventional ferroelectric memory and the cell array configuration. The memory cell configuration of the conventional ferroelectric memory is a configuration in which a transistor and a capacitor are connected in series. The cell array includes bit lines BL via which data is read out, word lines WL by which a memory cell transistor is selected and plate lines PL connected to drive one-side ends of corresponding ferroelectric capacitors. As shown in FIGS. 45, 46, in the ferro-electric memory, the memory cell configuration is a folded bit line configuration in which each memory cell is arranged in every two intersections of the word line WL and bit lines BL. Therefore, when the wiring width and the distance between the wirings are set to F, there occurs a problem that the minimum cell size is limited to 2F×4F=8F2.
Further, in order to prevent destruction of polarization information of the ferroelectric capacitor of the non-selected cell, it is necessary to divide the plate line for each word line and individually drive the plate line portions. In addition, since the individual plate lines are each connected to a plurality of ferroelectric capacitors arranged in a word line direction, the load capacitance becomes larger. Further, since the pitch of plate line drive circuits is set equal to that of the word lines and is extremely small, the size of the plate line drive circuit cannot be made large. For this reason, as shown in FIG. 47, the delay time at the time of rise/fall of the plate line potential becomes larger and, as a result, there occurs a problem that the operation speed becomes low.
FIG. 48 shows a configuration in which the plate line is commonly used. FIG. 49 shows a phenomenon of disturb generated by using the configuration of FIG. 48 and occurring in the ferroelectric capacitor of a non-selected cell. As shown in FIG. 48, the operation speed can be enhanced and the number of plate line drive circuits can be reduced by permitting cells connected to different word lines to commonly use the plate line and plate line drive circuit.
However, for example, when a word line WL0 is selected, the potential of a connection node of the plate line PL and the ferroelectric capacitor of a cell connected to a non-selected word line WL1 is raised from potential Vss to internal power supply potential Vaa at the active time by commonly using the plate line PL. At this time, the potential of a node SN1 of the non-selected cell is also raised to the potential Vaa by coupling of the ferroelectric capacitor. In this case, the potential of the node SN1 is set to a potential level which is slightly lower than the potential Vaa by the coupling ratio of a parasitic capacitance of the node SN1. However, there occurs no problem since the parasitic capacitance is smaller than the capacitance of the ferroelectric capacitor.
In this case, as shown in FIG. 49, if a long period of active time, a short period of standby time, a long period of active time, a short period of standby time, - - - are repeated, the potential of the node SN1 is gradually lowered due to a junction leak. As a result, when the standby time next occurs, the potential of the plate line PL is lowered to the potential Vss and the potential of the node SN1 becomes negative. When the standby time is long, the negative potential tends to be returned to 0V due to the junction leak or the like. However, in general, the active time is approximately 10 μs, the standby time is approximately 20 ns at minimum and the time ratio is 500. Therefore, the potential of the node SN1 is hardly returned to the original value and static disturb voltage is applied to the non-selected ferroelectric capacitor to destroy cell information.
Thus, the potential of the node SN1 is continuously lowered if the long-time active operation is repeatedly performed. However, when it becomes higher to some extent, the junction leak at the standby time occurs in a forward direction and the potential stops changing. Since buried-region potential is approximately 0.6V, the disturb voltage is set to approximately 0.3V. If a leak current from the ferroelectric capacitor is larger than the junction leak current, a lowering in the potential of the node SN1 is suppressed. However, even in this case, the two leak current amounts have their own distributions. That is, like the pause characteristic of the DRAM, a cell having a larger junction leak exists on the distribution due to the defect or the like. Further, in the ferroelectric capacitor, a cell having a small leak from the crystal boundary exists on the distribution. Therefore, a cell having two bad conditions imposed thereon exists and, as a result, polarization information is destroyed in some cells.
Judging from the above fact, it is difficult to attain the configuration of FIG. 48. As a result, the conventional ferroelectric memory has a problem that the plate line driving speed is low and the operation speed of the memory is low.
In order to solve the above problem, the inventor of this application proposed nonvolatile ferroelectric memories as described in “Jpn. Pat. Appln. KOKAI Publication No. H10-255483”, “Jpn. Pat. Appln. KOKAI Publication No. H11-177036” and “Jpn. Pat. Appln. KOKAI Publication No. 2000-22010”. According to the above ferroelectric memories (which are hereinafter referred to as memories of the prior applications), three points related to (1) memory cells of small 4F2 size, (2) plane transistors which can be easily formed and (3) high-speed random access function which is flexible can be simultaneously attained.
FIG. 50 shows the configuration of the memory of the prior application. As shown in FIG. 50, each memory cell is configured by one cell transistor and one ferroelectric capacitor which are connected in parallel and each memory cell block is configured by serially connecting a plurality of memory cells. One end of the memory cell block is connected to a bit line via a block selection transistor and the other end thereof is connected to a plate. With the above configuration, as shown in FIGS. 51, 52, memory cells of the minimum 4F2 size can be realized.
The operation of the memory with the above configuration is explained below. At the standby time, the potentials of all of word lines WL0 to WL3 are set at the high level to set cell transistors Q0 to Q3 in the ON state. Further, a block selection signal BS is set to a low level to set the block selection transistor into the OFF state. Thus, both ends of the ferroelectric capacitor are short-circuited via the cell transistor which is set in the ON state. As a result, no potential difference occurs between the two ends and polarization information of the memory cell can be stably held.
At the active time, only the cell transistor that is connected in parallel with the ferroelectric capacitor from which it is desired to read out information is set in the OFF state and the block selection transistor is set in the ON state. After this, the potential of the plate line PL is set to the high level so as to permit the potential difference between the plate line PL and the bit line BL to be applied only between the two ends of the ferroelectric capacitor which is connected in parallel with the cell transistor set in the OFF state. As a result, polarization information of the ferroelectric capacitor is read out onto the bit line.
Thus, even when the memory cells are connected in series, information which a desired ferroelectric capacitor holds can be read out by selecting a desired word line. That is, a complete random access operation can be performed.
Since the cell transistor of the non-selected cell is set in the ON state, the two ends of the ferroelectric capacitor of the non-selected cell are short-circuited via the cell transistor set in the ON state. Therefore, even if the plate line PL is commonly used by all of the cell transistors of the memory cell block, a problem of disturb voltage in the conventional ferroelectric memory can be solved. Thus, since the area of the plate line driving circuit can be increased while the chip size is reduced by commonly using the plate line PL, the high-speed operation can be realized. For example, if the plate line is commonly used by 16 cells, the product of the area of the plate line driving circuit and the delay time on the plate line can be reduced to 1/16 times.
In the memory of the prior application, the following problem occurs. The plate line PL can be used to realize an extremely high-speed operation. However, since read charges and write charges move between the cell transistor and the bit line BL via a plurality of cell transistors which are connected in series, delay components of the cell transistors occur. Therefore, the high-speed operation of the memory is limited. The delay time can be reduced by reducing the number of memory cells, but a merit of a reduction in the chip area is reduced to some extent.
As described above, in the conventional ferroelectric memory, there occurs a problem that the plate line cannot be commonly used, the high-speed operation cannot be attained and the cell size becomes larger. Further, in the memory of the prior application, there occurs a problem that the maximum speed is limited by the number of series-connected cells although the cell size can be reduced, the plate line can be commonly used and the high-speed operation can be performed.